[ List Subjects ][ Current Board ][ Post Message ]
Subject: Bay Area
[ View Followups ][ Post Followup ]
Date: 04/08/02 at 8:16 PM
Posted by: Vijay Tailor
PHYSICAL DESIGN PLACE AND ROUTE ENGINEER
Execute the physical design phase of COT ASICs.
Responsible for floor planning, place/route, timing optimization and verification of cell-based designs. Support early physical design consideration by product design groups through floorplanning and wire load
model generation. Help develop and refine physical design methodology.
MSEE/CS combined with 5+ years of related experience or BSEE/CS combined with 7+ yrs related experience.
Utilized Cadence or Avanti tools for the physical design of submicron designs.
Knowledge of HDL design flow and methodology, especially regarding synthesis and layout interaction.
Experience with designs including multiple blocks and gates.
Ability to develop scripts for tool control and UNIX manipulations.
Background of working with cross-functional development teams
SENIOR PLACE & ROUTE ENGINEER.
* Hand on layout and Place & Route.
* Floor planning, clock tree synthesis.
* Physical verification (LVS, DRC, Sizing).
* Generate post layout timing data.
* Support product development with all tape out activities for new and existing products.
* Archiving and documentation for each product.
* Provide technical support / communication with mask shop and foundries.
* Follow and improve back end methodology.
* 5 years experience in tape out and mask making activity.
* Avant! P&R tools, Milkyway.
* Physical verification using Dracula or Hercules
* Good communication skills
* Good programming skills preferred.
Ability to work with deadlines and maintain high quality standard.
Post a Follow-up: