World Leader in Engineering needs an EE with 3 years
experience in ASIC design for a temporary assignment.
The ideal candidate would have 2+ years of hands on
design experience of complex digital CMOS ASICS.
-Substantial experience with ASIC design tools
including VHDL, Mentor Graphics Quicksim, HDL Advisor,
Synopsys Design Compiler, and Behavioral Compiler
-Should be familiar with 1149.1 test standards
-Responsibilites include complex ASIC design,
architectural and detailed design, simulation,
feasibility testing, and worst case analysis