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Subject: Re: ASIC Design Engineers - San Diego

Date: 09/06/02 at 3:35 AM
Posted by: Ashwani Kumar
E-mail: ash_careers@yahoo.com
Message Posted:

In Reply to: Re: ASIC Design Engineers - San Diego posted by kalyani on 07/20/01 at 2:31 AM:

applying for the post of ASIC deesign engg.
my resume is as folows.

Flat No:- 3 B, Fairy lake Apartment
6-/907/12, Somajiguda , Rajbhawan Road,
Hyderabad 500082.
Phone Num:- 040-3309566.(PP)
E-mail: ash_careers@yahoo.com
ashwa77@yahoo.com
ASHWANI KUMAR

Total Professional 36 months
Experience:

ASIC Experience: 24 months

Career Review:

Company name : Sibar Software Services(India)Ltd.
Hi-Tech City, Cyber towers, Hyderabad.

Period : Currently working since 1st December 2000.

Designation : Design Engineer.

Profile : Currently working as ASIC Design Engineer.

Company name : Kamdar Tele Services Pvt.Ltd., Pune.

Period : Dec.1999 to July 2000.

Designation : Custom support engineer.

Profile : Maintenance & Installation of the "Key Telephone Systems". It is the Advance Version of the EPABX Systems.

Company name : Asur Engineers Pvt. Ltd.;

Period : July.1999 to Nov. 1999

Designation : R&D Engineer

Profile : Worked in the R&D team for the Customer Based Projects.

Projects Done:

1.Project Name : PCI Arbiter.
Project Duration : 1 month.
HDL Used : Verilog.
Skill Utilized : Mentor Graphics Tools.
Team size : 1.
Client : Sibar Software Services (India) Ltd.

Description :-
The PCI local bus is a high performance bus for interconnecting chips expansion boards and processor /memory subsystem. At any given time more than one PCI bus initiator device may require the use of the bus to perform a data transfer. Each PCI bus initiator device requiring the PCI bus, will assert a request signal REQ to the central PCI resource called the PCI arbiter. When a bus master needs a bus transaction, it asserts the bus request signal, REQn. If the ownership is not granted, REQn should be asserted by the master until the bus is granted. The Req is granted when GNTn to the master is asserted. Here I have implemented the ROUND ROBIN priority scheme to determine the priorities of the bus master. In this scheme the most recent requester that was granted the bus control gets the least priority and the requester next to it gets the highest priority and the other gets second highest priority.

2.Project Title : Link Layer controller for FIREWIRE(IEEE-1394).
Project Duration : 4 months.
HDL Used : Verilog.
Skill Utilized : Mentor Graphics Tools.
Team size : 4.
Client : Sibar Software Services (India) Ltd.

Description :
The features of this project are as follows:
Fully Interoperable with Firewire implementation of IEEE 1394 . it provides a Serial Bus interconnect interface that allows wide range of devices can be attached. Three modes of operation. The primary characteristics of this serial bus is Plug and Play ,easy to use and low cost implementation ,supports Isochronous and Asynchronous applications. The operation is Independent of the Host System.

My part was to design and development of the FIFO and the part of Isochronous module. Writing the code, functional verification and Synthesis.

3.Project Name : Data Encryption Standard algorithm using Verilog.
Project Duration : 1 month.
HDL used : Verilog.
Skill Utiliz : Mentor Graphics Tools
Team Size : 2.
Client : Sibar Software Services (India) Ltd.

Description
Block ciphers can be either symmetric-key or public-key. The main focus of this project is symmetric-key block ciphers; public-key encryption.
Block cipher definitions:
A block cipher is a function which maps n-bit plain text blocks to n-bit cipher text Blocks; n is called the blocklength. It may be viewed as a simple substitution cipher with large character size. The function is parameterized by a k-bit key K, taking values from a subset K (the key space) of the set of all k-bit vectors Vk. It is generally assumed that the key is chosen at random. Use of plaintext and ciphertext blocks of equal size avoids data expansion. To allow unique decryption, the encryption function must be one-to-one (i.e., inevitable).

My part in the project to develop the state machine for the algorithm, coding, writing test bench, Functional Verification.

4.Project Name : PCI Descriptor/ Status DMA.
Project Duration : 2 1/2 month.
HDL used : Verilog.
Skill Utiliz : Mentor Graphics Tools
Team Size : 1.
Client : Sibar Software Services (India) Ltd.

Description:-
The module takes the data from the data structures and according to the request from the host and the type of data transfer required (burst or normal) the data is given to the PCI burst scheduler.
The project was handheld independently by myself. Project includes a process, which interfaces with PCI burst scheduler and host. The Project included definition of I/O and developing state machine. The module contains a state machine to perform the interface between host and PCI burst scheduler. Coding was done in Verilog.

5.Project Name : 1 Gb Ehternet MAC IEEE 802.3ae.
Project Duration : 3 1/2 month.
HDL used : Verilog.
Skill Utiliz : Mentor Graphics Tools
Team Size : 5.
Client : Sibar Software Services (India) Ltd.

Description:
Under this project the data structure ware developed by our team members. My role in the project was to design a generic interface towards the application side and a flow control mechanism for the MAC transmitter.

6.Project Title : Universal Asynchronous Receiver Transmitter.
Project Duration : 1 month.
HDL Used : Verilog.
Skill Utilized : Mentor Graphics Tools.
Team size : 1.
Client : Sibar Software Services (India) Ltd.

Description
It provides serial communication between CPU & a serial device. This project is developed in Verilog. The features are as follows. It can operate on different baud rates by setting the value of transmit/receive clock divider. This is performed by most significant and least significant bit divide values into divlsb and divmsb register. Data is transmitted by writing the 8 bit value into the xmitdt register. Serial data is received into recvdt register. Any internal register can be read by CPU.A status register contains flags to indicate whether the transmission or receiving is in processing or completed.

My role in the project is from the whole project from design and development , writing the code , test benches, functional verification, and Synthesis.

7.Project Title : Programmable Peripheral Interface(8255).
Project Duration : 11/2 month.
HDL Used : Verilog.
Skill Utilized : Mentor Graphics Tools.
Team Size : 2.
Client : Helios Technologies.

Description:-
Development of core for the application using 8255A. Project is developed in Verilog. The features are: Three 8 bit peripheral ports: A, B, C. Three programming modes for peripheral ports. Mode 0(Basic input/output). Mode 1(strobed input/output). Mode 2(Bi-directional). All modes are set to input after reset. Total of 24 programmable I/O lines, eight bit bi-directional system data bus with standard microprocessor interface controls.

My part in this project is designing the different modes and top-level integration of 8255, and functional verification.

Academic Project :

1.Project Title : P.C to P.C Communication Using Fiber Optics.(B.E)
Team size : 2.
Role : Hardware Designing & Testing & Software.

Description
In today's world of communication speed is the important factor. In this project the data transfer takes place through Fiber Optics which has got very High Bandwidth and speed etc. as compare to the conventional Co-axial Cable. But the initial expenditure is High.

2.Project Title : BANK TOKAN DISPLAY.(T.E)
Team Size : 2.
Role : Hardware Designing & Testing.

Description
This project, was developed taking into consideration the Customer Convenience i.e. to avoid Queue in the Bank or Hospital. Here alarm facility to make Customer attraction towards the display when the Number changes.

Educational Qualification:

B.E (Electronics)
V.I.T college of Engineering Pune. (Pune university).

Professional qualification:

Completed a Diploma in VLSI Design at Helios Technologies, Pune.

Skills Set:
Operating Systems : Dos,Windows.
Programming Languages : C, assembly (8085,8086,8051).
Hardware Languages : Verilog,VHDL
EDA Tools : Mentor Graphics Tools for simulation
Synthesis & schematic, Xilinx, Active HDL.


Extra Curricular Activities:

NCC "C" Certificate.(Air Wing NCC).

Played "Volley-ball" in College team for three Consecutive Year.

Silver Medal in "Martial Arts(karate)" at Delhi in inter school competition.

Done Flying, Parasalling.

Hobbies:

Travelling, Reading Books, Playing Volley-ball, Swimming, making friends

Personal Details:

Date of Birth : 11th Aug. 1976

Marital Status : Single.

Languages Known : English, Hindi, Marathi.



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