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Our client is looking for FPGA(Field Programmable Gate Array) designers to work on a major effort to become the embedded technology supplier of choice for the world’s leading telecommunications and networking companies. The project is part of the effort to utilize FPGA designers to help develop a new line of CPU boards, communication interfaces(such as T1/E1 spans or fast serial ports) and protocol subsystems that can be sold off the shelf to customers so that their internal engineers and designers can utilize these platforms that’ll be used to develop chips to be used in mobile phones and telecommunications equipment.
Consultants or FPGA Designers(Field Programmable Gate Array) will be involved with designing Programmable Logic Chips, otherwise known as PLD’s. These PLD’s make up a high density field of gates called FPGA Architectures. The FPGA designers will be involved with designing a “gate array” which is an unfinished chip with electronic components that have not yet been connected. The designer will complete the chip by designing and adhering the top metal layers which provide interconnecting pathways. Once these chips are designed, then they’ll be turned over to manufacturing for mass production. These chips will make up final products such as CPU boards, communication interfaces, and protocol subsystems that will be used in the telecommunications industry.
There are a total of 9 groups for that have anywhere from 4 to 14 FPGA designers and Hardware Engineers that are working on the 3 major products for different customers. Submitted candidates will be placed in groups that need the most help. This is a cross functional project environment. Candidates will always work under a principal engineer. FPGA designers will track their performance and product development with Microsoft Project that will be reported to the head engineer.
PCI Hardware and Software
Embedded Hardware Design
3 years experience in the industry
View Logic (Schematic Capture Product)
Simulation Experience (Signal Quality or Timing Simulation experience)
Telecom Experience (T1/E1 Interfaces)
They use Power PC’s
Compaq PCI boards
Biggest Technical Challenge:
This is a very fast paced environment with large ongoing projects that have a make-up of multiple designers, engineers and tech leads. The candidate must understand and have experience with Power PC, PCI hardware and software, VHDL and embedded hardware design. If candidates do not possess these skills, it will be very easy to fall behind. There is no training involved. This is strictly heads down, chip design role.