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Subject: Re: ASIC Design Engineer

Date: 08/17/01 at 2:59 AM
Posted by: Ms. Sujatha
E-mail: brainet@hd1.vsnl.net.in
Message Posted:

In Reply to: Re: ASIC Design Engineer posted by azad singh on 05/23/01 at 3:54 AM:

Physical Design Engineers
**********************************************

A Graduate/Post-Graduate degree in
Electronics/Electronics & Communication
and a minimum of 2 years of ASIC Back End design experience.

Skills In:
0.18u/0.15u/0.13u VDSM technologies
. Floorplanning & Timing Driven/Datapath P&R
. Layout and full custom circuit designing
Pearl STA, Parasitic extraction
. Physical design verification (DRC, LVS)
Skills in C-Shell, Perl, SKILL scripting

Tools Exposure to:
Cadence Silicon Ensemble, Design Planner
IC-Craftsman, Pearl, Virtuoso, Spectre
or Avant! Aquarius, Apollo, Planet-PL
Cadence Dracula, Diva Assura or Mentor
Calibre or Avant! Hercules
. Cadence HyperExtract, Avant! Star-RC, Arcadia

May also have exposure to:
Synthesis using Synopsys/Ambit tools
. STA using Synopsys PrimeTime/Cadence Pearl.


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