| Home | Terms of Use | Site Map | Contact Us |
IndustryCommunity.com > Manufacturing Community > Jobs Forum > Message
Main Menu
Find

[ List Subjects ][ Current Board ][ Post Message ]
[ View Followups ][ Post Followup ]

Subject: Re: Digital Design Engineering Opportunities Available

Date: 07/20/01 at 2:48 AM
Posted by: kalyani.s
E-mail: kalyani_s_2000@yahoo.com
Message Posted:

In Reply to: Digital Design Engineering Opportunities Available posted by Brenda Stultz on 03/22/01 at 2:52 PM:

S.KALYANI
B.E ELECTRICAL & ELECTRONICS

ADDRESS:-

#9,Ekambaram street,
Old washermenpet,
Chennai-600 021.
Pager : 044-9628450719
E-mail:kalyani_s_2000@yahoo.com

CAREER OBJECTIVE:-

To work in challenging projects
involving complete design and coding to get myself
involved in the complete process of projects.The
challenging career involving the analysis,
designing,development and implementation.


TECHNICAL QUALIFICATIONS:-

P.G.Diploma In Digital Backend Design At ATIIT
Chennai

The course deals with all aspects of
V L S I,simulation and design of digital circuits ,knowledgeof hardware implementation languages like VHDL,VERILOG, parameter extraction, GDS II DATA generation.

Training On Tools:-
1.MODELSIM For Hardware Simulation
2.LEONARDO SPECTRUM for Synthesis
3.CALIBRE For Design Rule Checking,Layout Vs
schematic reporting
4.XCALIBRE For Parasitic Extraction


ACADEMIC PROFICIENCY:

Completed Bachelor of Engineering at Velammal Engg College,Madras University in the year 2000 with 72%

Completed HSC at ST.Mary's Matriculation Hr Secondary School, Perambur,Chennai in the year 1996 with 78.5%

Completed SSLC at ST.Mary’s Matriculation Hr Secondary School, Perambur,Chennai in the year 1994 with 74.3%

SOFTWARE SKILLS:

Operating Systems :Windows 95/98
Languages :C


PROJECT DETAILS:(B.E)

Project Title :STATIC RELAYS
Duration :Two Months
Description :The relays are
designed to cutoff the supply to system during
abnormal conditions such as high\low voltage,heavy
current.

PROJECT DETAILS: (PGDVLSI)

PROJECT1:-

Project title :Digital clock
Responsibility :design and development of
frontend&Back end.
Software tool :modelsim,leonardo,calibre,xcalibre.
Language :Verilog HDL.
Description :This digital clock consists of
four modes of operation.They are
Mode-1:For Normal Operation
Mode-2: For Time Setting.
Mode-3:For Alarm setting.
Mode-4:ForDate,Month,Year Setting.
Using later specifications the Project has been designed,synthesized,simulated.

PROJECT2:-

Project Title :Frequency Signal Generation in
Logarthmic Scale Using BCD
Counter.
Responsibility :design and developed Front
end&Back end.
Software tool :Modelsim,leonardo,calibre,xcalibre.
Languages :Verilog HDL.
Description :The frequency signals used in timing circuits are generated in Logarthmic
scale using BCD Counter.


PERSONAL DETAILS:


Husband’s Name :B.V.DINAKAR
Date Of Birth :12-05-1979
Present Address :#9,Ekambaram Street,
Old Washermenpet,
Chennai-21,
Tamil Nadu,
India.
Passport Number :B 2779648
Languages Known English,Tamil,Telugu.

Prof. J. P. Raina,
Formerly head for TV /IMAGE SIGNAL PROCESSING &
PHOTONICS IIT MADRAS
MD,Advanced Training Institute for Information
Technology,
No. 25, Yellow Pages Building,
RadhaKrishnan Salai,
Mylapore, Chennai-600004.
gargi@md3.vsnl.net.in

Place: Chennai

kalyani.s


Follow Ups:


Post a Follow-up:

Name:
E-Mail:
Subject:

Message to Post:

 

1999-2001 Sunlit Technology Co., Ltd. All rights reserved.