In Reply to: ASIC Design Engineers - San Diego posted by Don Thomas on 03/16/01 at 8:56 AM:
B.E ELECTRICAL & ELECTRONICS
Pager : 044-9628450719
To work in challenging projects
involving complete design and coding to get myself
involved in the complete process of projects.The
challenging career involving the analysis,designing,
development and implementation.
P.G.Diploma In Digital Backend Design At ATIIT
The course deals with all aspects of
V L S I,simulation and design of digital circuits ,knowledge of hardware implementation languages like VHDL,VERILOG,parameter extraction, GDS II DATA generation.
Training On Tools:-
1.MODELSIM For Hardware Simulation
2.LEONARDO SPECTRUM for Synthesis
3.CALIBRE For Design Rule Checking,Layout Vs
4.XCALIBRE For Parasitic Extraction
completed Bachelor of Engineering at Velammal Engg
College,Madras University in the year 2000 with 72%
Completed HSC at ST.Mary's Matriculation Hr Secondary School, Perambur,Chennai in the year 1996 with 78.5%
Completed SSLC at ST.Marys Matriculation Hr Secondary School, Perambur,Chennai in the year 1994 with 74.3%
Operating Systems :Windows 95/98
Project Title :STATIC RELAYS
Duration :Two Months
Description :The relays are
designed to cutoff the supply to system during
abnormal conditions such as high\low voltage,heavy
PROJECT DETAILS: (PGDVLSI)
Project title :Digital clock
Responsibility :design and development of
Software Tool :modelsim,leonardo,calibre,xcalibre.
Language :Verilog HDL.
Description :This digital clock consists of four modes of operation.They are
Mode-1:For Normal Operation
Mode-2: For Time Setting.
Mode-3:For Alarm setting.
Using later specifications project has been designed,synthesized,simulated.
Project Title :Frequency Signal Generation in
Logarthmic Scale Using BCD Counter.
Responsibility :design and developed Front
Software Tool :Modelsim,leonardo,calibre,xcalibre.
Languages :Verilog HDL.
Description :The frequency signals used in timing circuits are generated in Logarthmic
scale using BCD Counter.
Husbands Name :B.V.DINAKAR
Date Of Birth :12-05-1979
Present Address :#9,Ekambaram Street,
Passport Number :B 2779648
Languages Known English,Tamil,Telugu.
Prof. J. P. Raina,
Formerly head for TV /IMAGE SIGNAL PROCESSING &
PHOTONICS IIT MADRAS
MD,Advanced Training Institute for Information
No. 25, Yellow Pages Building,