| Home | Terms of Use | Site Map | Contact Us |
IndustryCommunity.com > Manufacturing Community > Jobs Forum > Message
Main Menu
Find

[ List Subjects ][ Current Board ][ Post Message ]
[ View Followups ][ Post Followup ]

Subject: Re: fpga / vhdl 18 month project

Date: 07/18/01 at 9:46 AM
Posted by: v.umashankar
E-mail: v_umashankar@yahoo.com
Message Posted:

In Reply to: fpga / vhdl 18 month project posted by Chris Nash on 10/18/00 at 1:15 PM:

CURRICULUM VITAE

V.UMASHANKAR
EMAIL : v_umashankar@yahoo.com

CAREER OBJECTIVE

Seeking a challenging career in the field of VLSI design in any organization, offering the opportunity to prove, utilize and enhance my skills.

EDUCATIONAL QUALIFICATION

Bachelor of Engineering in Electronics & Communication(1986-90)
First Class
Madras University.

TECHNICAL QUALIFICATION

Completed Course in FPGA conducted by Insight Memco., Bangalore.

Completed Course in VLSI design at Silex Logic Pvt. Ltd., Chennai.

Completed Course in Computer Networking & Internet Applications
Conducted by IIT-Kharagpur.

TECHNICAL SKILLS

Major Skill Areas : Writing codes for ASIC and FPGA modules.
Protocol : PCI.
HDLs used : VHDL and VERILOG.
Platform : Windows,Unix.

TOOLS USED :

Synthesis : LEONARDO SPECTRUM.

Simulation : MODELSIM,SILOS III,
ACTIVE HDL,PEAK VHDL.

FPGA : XILINX FOUNDATION MANAGER,ALTERA.

PROJECT DETAILS

1.PCI BUS TARGET

Company : Silex Logic Pvt. Ltd.,
Team size : 2 members
Duration : 2 months.

The PCI bus target is a bus interface unit designed for interfacing between a target device and PCI bus. It performs all the data transfer functions necessary for other PCI master devices to access data on the target device through the PCI bus. Write buffering and burst transfer is supported to maximize data bandwidth. All the PCI accesses to the target device are translated into a very user friendly X86 style back end interface bus. Data parity generation is handled automatically. All necessary PCI configuration registers are supported. Configuration accesses are processed locally without propagating into the back end interface.
In the essence, the PCI target device isolates the back end device from the complexity of the PCI bus and provides an efficient data pathway between the user device and the PCI bus system.



PCI BUS MASTER

Company : Silex logic Pvt. Ltd.,
Team size : 2 members
Duration : 2 months.
Language : VHDL
The PCI bus master is a bus interface unit designed for interfacing between a master device and PCI bus. It is capable of performing the initiator and target operations. It has efficient back end interface for different types of bus mastering devices. It supports burst transfer to maximize memory bandwidth. As a target device it supports target retries, disconnect and abort and as a part of initiator it automatically restarts the transaction during target retry and disconnect.
PCI master does the operation of memory read and write. The target holds the configuration registers for both PCI and OHCI.
My part is to write RTL code and analyze the functionality and test the modules for OHCI(Open Host Controller Interface).

2.UNINTERRUPTED POWER SUPPLY

Company : Tecconix Pvt. Ltd.,
Team size : 2 members
Duration : 2 months
Language : VHDL
Implementation: CPLD(XC-9574)
Macroblocks
Used : 69

This includes a/c mains sensing and stabilizing the input a/c. The chip monitors battery status continuously. It alarms if battery voltage is low and switch off the system.
It controls inverter output by PWM. It also alarms if the system is overloaded. The system displays the ac_input, ac_output and the error status.

3.8 CHANNEL TEMPERATURE SCANNER.

Company : Kalpana Lamps and Tubes., Ranipet.
Team size : 2 members
Duration : 2 months
Language : VHDL
Implementation: CPLD(XC-9574)
Macroblocks
Used : 57.

This system measures temperatures of 8 different boilers in 8 different locations. After monitoring the different temperatures it compares the data with reference data and switch off the boilers in extreme and low ranges.
It includes ADC, temperature sensing, amplification section, display section and control section to switch on/off of the boilers.

WORKING EXPERIENCE

1. Worked as Chief Engineer at Everest Marketing Ltd., from Jan-1991 to Jan-2000.
Nature of job:
Fault finding and servicing of Facsimile Telecopier, Panaboards and microdocumentation machines.
Designed a circuit to detect incoming calls and to power on Facsimile Telecopier.

2. Worked as FPGA Trainee Design Engineer at Insight Memco., Bangalore from March-2000 to May-2000.
Nature of job:
Syntax verification ,simulating and programming the CPLD chips.

3. Working as ASIC Design Engineer Trainee at Silex Logic Pvt. Ltd., from June-2000 to till date.
Nature of job:
Analyzing the specification ,writing and verifying the coding.


PERSONAL INFORMATION

Name : V.UMASANKAR
Fatherís Name : L.VENUPILLAI
Date Of Birth : 02-06-1969
Place of Birth : CHENNAI
Marital Status : MARRIED
Languages Known : ENGLISH & TAMIL.

PERMANENT ADDRESS

Old No:15,New No:35,Agraharam Street,
Chintadripet,
Chennai-600 002.
Tel : 91 44 8588771.



Follow Ups:


Post a Follow-up:

Name:
E-Mail:
Subject:

Message to Post:

 

1999-2001 Sunlit Technology Co., Ltd. All rights reserved.