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Subject: Re: ELECTRONIC ENGINEER JOB AVAILABLE (SAN LUIS OBISPO, CA) WITH ERNIE BALL
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Date: 07/13/01 at 11:54 PM
Posted by: bryan ranger
In Reply to: ELECTRONIC ENGINEER JOB AVAILABLE (SAN LUIS OBISPO, CA) WITH ERNIE BALL posted by Don McCaleb on 05/18/01 at 2:04 PM:
I am searching for a contract hardware position. Onsite or offsite (manage thru daily progress report/scheduling, and video conferencing). Attached is my resume. Reviewing it will show some audio experience.
FPGA/DIGITAL AND FIRMWAVE ENGINEER
FPGA Tools: Cadence Leapfrog, Synopsis FPGA Express, Orcad Express, Viewlogic Workview/Powerview, Mentor Graphics Dmgr/Qvhdl/QsimII/DA, Xilinx M1.5 Foundation/XACT 5.2, Dataio Synario, Altera MaxPlus2
Circuit Design: FPGA’s. Microprocessor, EPROM, DRAM, simulation, schematic capture, instrumentation amplifiers, PLD’s, FPGA’s, low level sensor analog, SMD design, supervised PCB layout
Military Electronics Companies: Rockwell, McDonnell Douglas, Litton, T.I.
Instruments: Emulators, logic analyzers, scopes, universal programmers
Hi-level languages: C, PLM, BASIC, FORTRAN, ATLAS
Assembler: 8086, 8051, Z180, PIC16CXX & 17C42, Z8000, 8048, COP800
Engineer responsible redesigning an avionics VME motherboard for Saab using Mentor Graphics netlist. Converted the netlist over to Orcad Express. Developed FPGA module spec for a Vertex2 electronic warfare range generator.
Engineer responsible supporting design and test after engineering layoff. Product was a VME based data logger with Altera FPGA's and EPLD's.
Actel Design Services
Engineer responsible for designing 24 channel fast ethernet board using MMC Gigbit network switch. Generated spec for 2 channel gigabit board using same MMC part.
Engineer responsible for redesigning IO board with 1553 processor, six RS422 channels and a Xilinx 9500 CPLD. The CPLD had a watch-dog timer, decode logic, clocks, and clock monitor coded in vhdl. Performed 3rd generation design with Xilinx 4000 series FPGA, PCI core, and the above features.
Engineer responsible for upgrading an Actel CPLD to a radhard 8085 satellite controller using Orcad 9.5. For backward compatibility the design was schematic but the testbench was in VHDL.
Engineer responsible for upgrading three Xilinx XC4010 FPGA’s in VHDL and schematics on the dwell controller card of an EW system. The board and FPGA’S were simulated using Mentor Graphics QVHDL/QSIMII. Other FPGA tools Design Architect, Xact 5.2, and Synario
Engineer responsible designing for a Xilinx XC4028 FPGA in VHDL to interface SRAM , timer, interrupt controller, and Z8000 bus emulator modules to the PCI bus. Fpga tools used were Cadence Leapfrog, Synopsis FPGA Express, Orcad Express, Viewlogic Workview, and Xilinx M1.5 Foundation.
Engineer responsible for designing modules in Altera 10K series FPGA's using MaxPlus2 for an MPEG encoder and decoder board sets. Additional tasks included testing prototypes and pilot production.
Engineer responsible for upgrading a Xilinx 4000 series fpga with a pattern searching algorithm and VME interface to a time division-multiplexing card. Tools used on the VHDL program were Viewlogic and Synopsis.
Project engineer responsible for designing an ARINC 561 input/output board (using eplds with ABEL, Viewlogic, and VHDL) and directing firmware development using an 8051 based ASIC with dual port ram and MIL-STD-1553 bus controls. The firmware was upgraded from a previous version to include the new ARINC 561 serial transmitter, built-in test features, and monitor for board testing. The board is part of the Cntrl and Display Unit of the nav- system.
Hardware and software engineer responsible for a wireless trunking console used in communications between company vehicles. The Microchip based PIC16C74 console uses a real-time kernel in assembly and the application software in C. The hardware consists of a Xilinx's EPLD, DTMF transceiver, microcontroller level setting buffers using the PWMs, software real-time clock, LCD display, and a keyboard.
Project Engineer responsible for conceptual and analog design; software coordination; SMD PCB coordination; and scheduling of the dual humidity and temperature transmitter using the Microchip 16C71. The 16C71 is used to read the RTD and humidity sensors through the instrumentation amplifiers designed with inexpensive op amps. The temperature and humidity readings are then used as an index into a lookup table. The 16C71 outputs two PWM’s for the humidity and linearize the RTD to drive the 4 to 20ma current loop.
Responsible for design of a memory board for a CD quality stereo format and cassette tape MOH digital repeater with a phone interface.
Responsible for the design of the multiple channel digital repeater/controller, which consisted of a network controller, 4-wire serial bus, 16 memory bus units, and 4 audio bus units. The repeater's messages (stored in EPROM's) were transmitted from memory units over the serial bus at 4M baud to one of the 4 audio units. All bus devices were based on the 17C42 controller except for the Z180 bus controller. The program for the bus units consisted of the bus protocol and the application software, which were written in assembly. The rest of the memory and audio bus units software consisted of managing the ADPCM data requests and controlling the ADPCM signal processor respectively. The Z180 program, in C, issue commands to play message X from memory bus unit Y to audio bus unit Z. The task chart to be used by CMK’s real-time kernel defined the Z180 tasks.
Project Engineer responsible for the design of the programmable gate array (PGA) in a Safe and Arm Fuze (SAF); integration of HV power supply; and coordination of the housing design, safety studies, and product reviews. The SAF arms and fires the warhead after the proper handshaking from the avionics. The SAF consists of the interface circuitry, HV power supply, and fire circuitry. Design and simulation of the PGA was performed with Viewlogic's CAD program.
Software Engineer responsible for writing software for a microcontroller based SAF and integrating it with the HV power supply.
Design Engineer responsible for design of a test board used to validate the fiber optics in the Harden Mobil Launcher; a Laser based ordinance system. The test board was designed first with an 80C51 then was redesigned because of hardening using PAL's to control the laser distributor and used C to model some analog components.
Software Test Engineer responsible for 8051 software development on a tape drive head tester. The existing table driven software for 9610 Pertec tape drive was modified to test the head of the tape drive.
Test Engineer participated in training technicians and integrating test systems for the Army. Each system consisted of 4 equipment racks installed into a shelter.
Engineer participated in writing Z8000 assembly language program for a tape drive cache and 8051 formatter, designed a PC test card to control tape drives, and performed software qualification tests for the tape drive cache.
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