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Subject: Re: ASIC (FPGA) Engineers in the UK

Date: 07/10/01 at 12:44 AM
Posted by: jaganathan gnanavelu
E-mail: jaganathang@rediffmail.com
Message Posted:

In Reply to: Re: ASIC (FPGA) Engineers in the UK posted by NANDAKUMAR.P on 04/08/01 at 4:28 AM:

Resume of JAGANATHAN G

Career Objective:
Why don't I be the member of your winning team?

Professional Experiences:

Having 1years of Domestic Experience in VHDL and ASIC

Academic Qualifications:
M.E. (Electronics) from MIT Campus ANNA UNIVERSITY(Aug 1999-Feb 2001), Madras,
Tamil Nadu, India.

B.E. (Electronics and Communication )from Government College of Engineering
(1994-1998), Tirunelveli, Tamil Nadu, India.

Language Proficiency:

Operating Systems : Windows NT, 9x, DOS
Assembly Language : ADSP21XX, ADSP2106X(SHARC)
Software Language : C, c++
Hardware Language : VHDL, Verilog
Tool : MATLAB 5.3

Project details:

#1
Duration : July 1998-Dec 1998
Employer : Vdesign Private Ltd, Pondicherry, India
Title : FPGA implementation of Qaudrature Mirror Filter

Description:
Qaudrature Mirror filter are used in many speech and communications
application.In coming signal has split into two subbands. Each band speech
signal Passes through FIR low pass filter , down sample signal , up sample and
then low pass Filter.

#2
Duration : Jan 1999-June 1999
Employer : Vdesign Private Ltd, Pondicherry, India
Title : VHDL implementation of ADSP21xx DSP


Description:
The objective of the project is to implement FPGA design for ADSP21xx DSP
Processor.ADSP 2100 family is a16 bit, fixed point machine.Most operation assume
a twos complement number representation, while others assume unsigned numbers or
simple binary strings.In this project we have designed ALU, DAGs(Data Address
Generators), MAC(Multiply and Accumulator) and Shifter for 16 bit DSP Processor.
ALU performs arithmetic and logical operations. DAGs generates program memory
and data memory address. MAC performs multiplication and accumulation.
Shifter performs arithmetic and logical shifts.


#3 ME Project:
Title: Vhdl and Dsp implementation of Viterbi decoding
client:Comit System Inc.

Description:
The performance of modern digital communication system are often restricted due
to the powder limitation and presence of AWGN.The addition of forward error
correction to transmitted digital waveforms overcomes these limitations.One of
the most efficient FEC technique employs a combination of Convolutional encoding
and Vitebi decoding.
In the Transmitter section encode the serial input data bits by Convolutional
encoder of rate 3/4 and Constraint length K=9.
In the Receiver section decode the received data bits by soft decision Viterbi
Decoding. Received data bits compared with all possible states and also finds
hamming distance. Find the minimum hamming distance and trace back through the
trellis that will give original message.
This project has implemented both in vhdl and SHARC DSP processor.
Personal Details:


Date Of Birth : 1st Feb 1976

Marital Status : Single

Email: : jaganathang@hotmail.com

jaganathang@rediffmail.com


I here by declare that the above mentioned all the details are true and correct
to the best of my knowledge and belief.

Place:

Date: (JAGANATHAN G)


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