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Subject: Re: Sr. ASIC Designer in Eastern Washington

Date: 06/23/01 at 1:29 PM
Posted by: subash chandra bose
E-mail: vsubash@usa.net
Message Posted:

In Reply to: Sr. ASIC Designer in Eastern Washington posted by Valentina Kalnitsky on 06/22/01 at 5:09 PM:

Email: vsubash@usa.net


To obtain a challenging position in ASIC/FPGA design.


About 1.5 years of experience in ASIC and FPGA design.

Worked as Design engineer in of VDESIGN Pvt ltd., pondicheery currently
employed Member Technical staff CMOS CHIPS, Bangalore.

Designed reusable IP blocks for ASICs and FPGAs using Verilog HDL, VHDL
and Leonardo Spectrum synthesis tools. Highlights of the experience are:

.Expertise in reusable ASIC and FPGA Designs
.Expertise in ASIC and FPGA Synthesis
.Experience in FPGA Frontend.
.Strong in Networking fundamentals PCI,PCI-X,USB,SONET,Ethernet
.Experience in test environment development for ASIC and FPGA
.Real time experience in Verilog, VHDL, Vera, Unix Script.

EDUCATION (1995- 1999)

Bachelors degree in Electronics and Electrical Engineering from University
of madras, India. Graduated in July 1999 with aggregate of 66%.

Projects Summary:

Project 1:April 2000 - till date(CMOS CHIPS-Bangalore)

SONET:Synchronous Optical NETwork :

At present working in this project.

Project 2:Oct 2000 - Dec 2000 (CMOS CHIPS - US)

PCI Controller Core :

The PCI Controller Core is an implementation of a host bridge that supports
a generic Host sitting on one side of the controller while the other side of
the controller is fully compliant to the PCI 2.2. The PCI Controller
appropriately handles all the transactions initiated by the host at the
Host-Controller interface. Similarly a request initiated by a PCI device,
sitting on the bus, for a transaction with the Host device is also processed
through the PCI Controller Core.

.Verified PCI Controller Core.
.Developed the testcases using VERA
.Coverage analysis and suggestions for RTL improvement
.Responsible for finding bugs and try to fix it.

Tools Used : VERA(Synopsys), Simwave.
Languages Used : Vera.

Project 3:JAN 2000 - FEB 2000 (CMOS CHIPS - US)


Orthodeflector - Swath FPGA:

Swath FPGA is one of the 3 FPGA in Ortho deflector receives swath data from
LINK II FPGA in the proper format and send it to Print FPGA.
.Developed Test plan and test table for Swath FPGA.
.Developed test environment for Swath FPGA.
.Developed testbenches in verilog for Swath input module.
.Helped designers to modify RTL .
Tools Used : Verilog-xl, Simwave.
Languages Used : Verilog.

Project 4: NOV 1999 - JUN 2000 (Vdesign - pondicheery)

PCI BUS Interface with CAN Controller:

The PCI bus is designed for high performance data transfer between system
memory and peripherals maximum transferring rate of 32 bit PCI is 133Mbps.
Controller area network(CAN) is used for automation of general industrial
In this project we are involving to interface PCI bus with CAN Controller.

.Designed target model for PCI Bus in VHDL.
.Developed testbenches to test the Unit level testing.
.Simulated and checked the waveforms and debugged the errors.
.Designed the CAN Controller transmitter frame.
.Tested for proper functionality.
Tools Used : Modelsim, Leonardo Spectrum, Design Manger.
Language Used : VHDL.

Project 5:
Four-bit Microprocessor : Training Project.

In this four bit processor consists of the following components such as
Multiplexer, program counter, register, Instruction decoder, Arithmetic and
logic unit, Memory(Ram and Rom) and Timing and control. For this blocks VHDL
coding and Testbenches were written.


.VERA - Synopsys.
.Verilog-XL -Cadence
.Modelsim EE 5.2C(FLI)
.LEONARDO Spectrum
.Design Manger - Xilinx Place and Route.

Contact Address : C - 29/26, Mohan nagar,
Salem - 636 030.

Phone Numbers : +9180 5544613 (home)
+9180 8520170/+9180 8520180 (office)

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