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Subject: Re: ASIC Design Engineer

Date: 05/23/01 at 3:54 AM
Posted by: azad singh
E-mail: azad_nim@usa.net
Message Posted:

In Reply to: ASIC Design Engineer posted by HarryS on 03/19/01 at 4:33 PM:

RESUME
----------

Name: AZAD SINGH

Sex : Male

Date of Birth: 15-08-1975

Correspondence
Address:
B-228 Sanchar Vihar, ITI Township. Mankapur,
Dist. Gonda (U.P.),
Pin -271308 India.

Telephone: 05266-84428 (Office) Between 8 A.M.- 4 P.M., 05266-84640 (Res.)

E-mail: azad_nim@usa.net


Professional Qualification

(a) Name of Institute: University of Roorkee, Roorkee (U. P.) India.
(b) Course : B. E.
(c) Year of passing : 1998
(d) Percentage : 72 %


WORKING EXPERIENCE

1. Aug 1999 - Present: Assistant Executive Engineer in ITI ltd.- One of the telecom
giant of India for total telecom solution.
2. May 98 - Aug 1999 : Associative Member of Technical Staff - Duet technology ltd. -
Duet tech is involved in Front end and Back end of VLSI design.


Academic Achievements
- Received scholastic certificate in school
- Received scholastic certificate in college for outstanding performance.

Extra- curricular Achievements
- Active participant in electronics hobby center in University of Roorkee.
- Active participant in Badminton.


MAJOR ASSIGNMENTS UNDERTAKEN

Present assignment

-Development of terminal Interface card tester for C-DOT DSS MAX-L.
Team size: 01
Development platform: 1. CDOT -DSS MAX processor unit.
2. Shell Scripting on Unix platform.
Responsibilities: Study the role of terminal interface card (TIC) which is
mainly involved in interfacing subscriber time slot with
the main time switch unit and accordingly developed the
hardware and software for the tester.


Others

-Generation of library (including cells like RAM, ROM, MEMORY, LUTís) using following
languages and tools.
1. VERILOG
2. VHDL
3. SYNOPSYS
4. TLF (Timing library format - Timing format generated by cadence tool)
Duration : 5 months
Team size: 01
Development platform: Verilog, VHDL, and Synopsys -Design Compiler, Design Analyzer.
Cadence - wave analyzer.

-Synthesis of given VERILOG and VHDL designs by Synopsys -Design Compiler.
Duration : 4 months
Team size: 01
Development platform: Verilog, VHDL, and Synopsys -Design Compiler, Design Analyzer.
Cadence - wave analyzer


-Design and testing of a TMS-320 based Real time implementation of ADPCM, 16-QAM OFDM
(ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING) Modem.
Duration : 1 and 1/2 months.
Team size: 03
Development platform: 1.TMS-320 Processor kit (By Texas) for the calculation of FFT.
2. Additional hardware for analog filters.
Role: Team member


-To convert a given VERILOG and VHDL library in mentor graphics format.
Duration: 2 and 1/2 months
Team size: 02
Development platform: Verilog - XL (for simulation), Mentor -Design analyzer.
Role: Team member.

-Generation of an automation tool for comparing the output generated after simulation
of Verilog,VHDL etc.
Duration: 2 and 1/2 months
Team size: 01
Development platform: C, PERL, and UNIX.

TRAINING ATTENDED
Two weeks training on VERILOG, VITAL and synthesis (BY Synopsys DC ).
Two weeks training on design analyzer (Mentor Tool - used for generating design in
symbol form).
Two weeks training on SILICON ENSEMBLE (Cadence tool- used in back end design)
Two weeks training on Fundamentals of Digital Electronic Exchange.
Two weeks training of C-DOT DSS (Exch. Level &Card level) at C-DOT, Bangalore.


PROFESSIONAL SKILLS
Proficiency in --
PERL, Verilog, Shell-Programming, HSPICE
Synopsys - Design compiler, Design analyzer
Cadence - Verilog-XL, Wave analyzer

Programming skills with C.
Knowledge of Digital Electronic Switching System.


Azad Singh


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