Design Verification Manager (Permanent)
The Design Verification Manager I responsible for pre-silicon functional verification of ASICs. This is a highly visible position for the right candidate who has a desire to make a big impact.
* Implementing and evolving best-in-class design verification methodologies.
* Building a strong DV team.
* Creating and implementing project-specific DV plans.
* Creating the RTL simulation environment for block and chip level functional verification.
* Creating simulation models using Verilog or PL1 based models written in C.
* Managing the development of functional tests for multi-processor embedded architectures with integrated intelligent bus masters.
* Implementing advanced DV techniques such as pseudo-random testing, functional stress testing, regression triage, hardware emulation and formal verification.
* BSEE or equivalent (MSEE preferred).
* Eight or more years experience in ASIC/IC design or design verification.
* Experience with Cadence and/or Synopsys synthesis-based front-end IC design tools.
* Experience creating BFMs using Verilog and/or C via PL1.
* Expert user of Unix and Unix utilities.
* Proven track record manging small teams and leading DV projects.
* Excellent communication skills and ability to work effectively with others.
* Desire for challenging work and high visibility.
* Desire to work hard, play hard and pre-IPO stock options!
And someone with this background will definitely get our attention:-
* FPGA or hardware emulation experience.
* Programming experience with Perl, C, C++.