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Subject: ASIC Engineers- Telecom chip

Date: 04/11/01 at 2:14 PM
Posted by: Joseph Perera
E-mail: josephp@bradson.com
Message Posted:

We are looking for a senior ASIC Design Engineer with Master's in EE with at least 4 years of experience in digital Design with deep sub micron. Verilog , Ethernet, IP or network Processor.

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