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Date: 02/08/01 at 10:13 AM
Posted by: SUNDARESAN.V.M.
E-mail: vm_sundaresan@hotmail.com
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In Reply to: ASIC (FPGA) Engineers in the UK posted by Steve Banks on 01/31/01 at 6:58 AM:
CURRICULUM VITAE
V.M.SUNDARESAN
#18, Haripradeep Apartment,
1st Cross street, Rayala Nagar,
Ramapuram, Chennai-600089.
Phone: 091-44-2491958
Email: vm_sundaresan@hotmail.com ______________________________________________________________________
OBJECTIVE:
To be part of an organization that provide a very good
environment to contribute and diversify one's knowledge and skills and
to work in a challenging and innovative asic projects.
PROFESSIONAL EXPERIENCE:
COMPANY
H.S.N. Solutions Pvt. Ltd.,
Chennai.
Working as a Design Engineer Trainee from May 2000 - till date
WORK PROFILE:
PROJECT SUMMARY:
COMMON SWITCHING INTERFACE (CSIX-L1):
HDL Used : VHDL
Duration : 2 months
Team Size : 2 Member
Role : I had been involved in the Design and coding of
the assignment.
SYNOPSIS :
Designing a Common switch interface for high-speed
repeaters involves the interface between a traffic manager and a
switch fabric, for data transfer applications. This includes C-frame
generator, and addressing system for the flow control.
ETHERNET INTERFACE OPTOELECTRONIS SWITCH CONTROLLER:
HDL Used : VHDL
Duration : 3 months
Team Size : 1 member
Role : I have been involving in the Design and coding
of the assignment.
SYNOPSIS:
The optoelctronics was developed to transfer data at
very high speed and with low interference . The switch controller is
an ethernet interfaced device that controls the optoelectronic switch.
This switch has been designed in a master-slave configuration and is
capable of controlling switches orientated in a 16 input X 16 output
configuration. The instruction for the switch controller is obtained
from the ethernet packet.The switch controller can be summarized into
INTEGRATED SYSTEM, MASTER CONTROLLER AND SLAVE CONTROLLER.
DUART (DUAL UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER):
HDL Used : VERILOG
Duration : 2 months
Team Size : 2 Member
Role : I have been involving in the Design and coding
of the assignment.
SYNOPSIS:
The DUART is usually a programmable for implementing
asynchronous serial communication. The receiver converts serial data
bits received on the line into parallel bytes. The transmitter
converts the parallel bytes into serial bits to be sent on the line.
The frequencies of the transmit clock and receive clock need not be
equal. But the baud rate of the sending end transmitter should be
equal to the baud rate of the receiving end receiver.
EDUCATONAL QUALIIFICATON:
Bachelor of Engineering
(Electrical & Electronics Engg)-2000.
MADURAI KAMARAJ UNIVERSITY
ACADEMIC PROJECT:
ECG SIGNAL TRANSMISSION THROUGH TELEPHONE LINE
SYNOPSIS:
To provide an interface to connect the ECG (the patient)
in a remote place and a doctor in a different destination. The
interface consists of transmitter and a receiver. The transmitter is
connected to the ECG instrument .It transmits signal through the
telephone line. The receiver is connected to the telephone line in
a distant destination. The doctor is able to monitor his patients
from a distant destination .The receiver part is controlled by a
microprocessor (8085) to differentiate the normal telephone signal
to the transmitted ECG signal.
COMPUTER SKILL SET:
Hardware Languages : VHDL, Verilog HDL.
Tools Used : Model Tech's V-System Simulator,
Veriwell,
WARP ,
Silos III,
Active HDL.
Editors : Vi
Operating Systems : MS-Windows, MS-DOS, UNIX
PERSONAL DETAILS:
Father's Name : Mahendran.V
Date of Birth : 30th of March,1979
PROFESSIONAL SKILLS:
* Have ability to work with others, build good relationships and
function well as part of a team.
* Enthusiastic, Innovative, plan and control to meet deadlines.
* Have communication and team management skills with
Willingness to learn.