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Subject: Why does AMD 486DX2/4 want clock grounded at power-up?
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Date: 10/20/00 at 8:24 AM
Posted by: Gerald Bremer
AMD has an application note on their web site that recommends maintaining the 486DX2/4 CLK input at ground level until VCC is valid after power-up. Does anyone know why this is necessary? Our design keeps the 486DX reset
for >500ms after power-on. It seems like this would give the 486's phase-lock-loop plenty of time to lock into the correct frequency before reset goes inactive. Why do they also want the CLK input grounded until VCC is valid? AMD doesn't mention this requirement in their data sheet. It is
only mentioned in an app. note, which is why I question if this is necessary.
I won't go into details, but I can modify our design so that the 486's CLK stays static at a high level (where is rises with VCC) for 250ms after power-up. Would this be just as effective as AMD's recommendation to "ground" the CLK input?
We have used the Intel and ST 486DX2/4 parts in the past, but the AMD parts use less power and have better availability (ST486DX4 has been end-of-life'd). Intel and ST didn't have this clock gating requirement. I have been trying for 3-weeks to get AMD to answer questions about this, but I think their tech. support has forgotten the reasons behind their app. note.
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