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Subject: SCC AMD 85C30 challenge

Date: 07/30/00 at 7:12 PM
Posted by: Julio
E-mail: juliop@microsol.ie
Message Posted:

We have been experiencing problems in our comms due to an error in our SDD
85C30 in noisy environments.

Our 1200baud modems produce spurious pulses at the end of transmission which
go directly into the SCC AMD 85c30 Channel B Rx. Those pulses could come 20 or
30 ms after the last transmitted byte. The general shape of them consist of a first
spurious of 8-12ms that produces good chars, chars with parity error or
occasionally framing error. The break condition i s detected as well.


1-2ms after this pulse comes another smaller ones of half a bit duration
(360-440ms) that occasionally makes the 85c30 to lock up one or two bits in the
receive shift register. The FIFO is emptied and cleared every time an interrupt is
generated.

The hypothesis of the lock up in the receive shift register comes from the
characters read when eventually this problem happens. The next character coming
in the Rx pin hundred of miliseconds later(IMPORTANT: always 0x68 c learly seen
in the oscilloscope) comes as:

(Format: Start(1), byte(8), Even Parity(1), Stop(1))
- 0xD0: with parity error that is, 0 0000 1011 0 1
- 0xA0: with framing and parity, 0 0000 0101 1 0
- 0xA1: with framing error, 0 1000 0101 1 0

Seeing that 0x68 is 0 0001 0110 1 1, it looks like that some bits get stuck into the
receive buffer during the last pulse, then the clock gets locked up and the shift
register bit counter remains pointing to the second or t h ird bit in the receive shift
register.

I can not prevent this from happening. This problem is hammering us.

I have contacted AMD Tech Support and I have not had a word so far.

If anyone has experience with this device or is aware of any problems please reply.

Regards,
Julio


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