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Subject: 8051 and IO decocding
Posted by: Nicholas Parker
E-mail: NRPARKER(at)XTRA(dot)CO(dot)NZ(no spam)
Can anyone offer me a good system for memory mapped IO on an 8051. I want to waste minimal address space and have no extra logic other than my input and output latches (digital IO) and a PLD.
I have thought of just a PLD and think that this with some 573 latches and the appropriate eqns might work. I want 32kb boot/monitor ROM, 64 k RAM (minimal wastage.) upper 32k ram is to be Von Neuman (i.e.overlapped by /PSEN AND /RD) equivalent. latches are to map into upper half of ram at top.
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