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Subject: Low power logic design
Posted by: Nigel Cumberland
E-mail: NCTecs(at)aol(dot)com(no spam)
Can anybody help
I am designing a very low powered circuit using a simple CMOS logic circuit
interface to a series of SPST switches. I need to keep the current consumption very low for battery applications. Please can anyone advise as to what the maximum value of pull up resistor I can use for a switch input is. The logic gates will probably be 4000 series or even Arizona Microchip PIC16C711 microcontrollers.>
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