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Subject: High speed CMOS design

Date: 08/01/99
Posted by: Prakash Pynadath
E-mail: pyna6me(at)ccs(dot)iitb(dot)ernet(dot)in(no spam)
URL: http://


I am a VLSI design engineer. I am trying to design Network hardware like routers and packet switches using CMOS logic. I am trying to achieve speeds of tera bits per second. Such high speeds will probably require asynchronous architectures. So if you can suggest me any reference material on asynchronous architectures, simulation of asynchronous architectures and very high speed CMOS design issues, please kindly let me know.

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